Integrated Formal Analysis of Timed-Triggered Ethernet

نویسندگان

  • Bruno Dutertre
  • Natarajan Shankar
  • Sam Owre
چکیده

We present new results related to the verification of the Timed-Triggered Ethernet (TTE) clock synchronization protocol. This work extends previous verification of TTE based on model checking. We identify a suboptimal design choice in a compression function used in clock synchronization, and propose an improvement. We compare the original design and the improved definition using the SAL model checker.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Performance Analysis of Industrial Ethernet Networks by Means of Timed Model-checking

Ethernet networks are promising for the harmonization of the communication technologies in manufacturing automation but they have not been specifically intended for industrial control applications. Investigations have thus become necessary to evaluate their performance. Most analysis approaches use probabilistic models to validate the system’s behavior. However, if the deterministic behavior of...

متن کامل

Case Study: Model Transformations for Time-triggered Languages

In this study, we introduce a model transformation tool for a time-triggered language: Giotto. The tool uses graphs to represent the source code (Giotto) and the target (the schedule-carrying code) of the transformation, and has been implemented entirely using graph rewriting techniques. The meta-models of the input and the output were specified using standard (UML) technology, and the transfor...

متن کامل

Six Issues in Testing Event-Triggered Real-Time Systems

Verification of real-time systems is a complex task, with problems coming from issues like concurrency. A previous paper suggested dealing with these problems by using a time-triggered design, which gives good support both for testing and formal analysis. However, a time-triggered solution is not always feasible and an event-triggered design is needed. Event-triggered systems are far more diffi...

متن کامل

Business Process Verification: The Application of Model Checking and Timed Automata

The most important result to standardize the notation for graphical representation of Business Processes (BPs) is the Business Process Model and Notation (BPMN). Despite the BPs modeled with BPMN being able to support business designers, BPMN models are not appropriate to support the analysis phase. BPMN models have no formal semantics to conduct qualitative analysis (validation and verificatio...

متن کامل

Modular verification of timed circuits using automatic abstraction

The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into modules, each with constrained complexity. Before verification is applied to each individual module, irrelevant information to the behavior of the se...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2012